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Correct Hardware Design and Verification Methods 10th IFIP WG10.5 Advanced Research Working Conference, CHARME'99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings

Aus der Reihe Lecture Notes in Computer Science

49,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

15.09.1999

Abbildungen

XII, 376 p.

Herausgeber

Laurence Pierre + weitere

Verlag

Springer Berlin

Seitenzahl

376

Maße (L/B/H)

23,5/15,5/2,1 cm

Gewicht

587 g

Auflage

1999

Sprache

Englisch

ISBN

978-3-540-66559-5

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

15.09.1999

Abbildungen

XII, 376 p.

Herausgeber

Verlag

Springer Berlin

Seitenzahl

376

Maße (L/B/H)

23,5/15,5/2,1 cm

Gewicht

587 g

Auflage

1999

Sprache

Englisch

ISBN

978-3-540-66559-5

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: ProductSafety@springernature.com

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  • Produktbild: Correct Hardware Design and Verification Methods
  • Produktbild: Correct Hardware Design and Verification Methods
  • Invited Talks.- Esterel and Jazz : Two Synchronous Languages for Circuit Design.- Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications.- Proof of Microprocessors.- A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer.- Formal Verification of Explicitly Parallel Microprocessors.- Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic.- Model Checking.- Model Checking TLA+ Specifications.- Efficient Decompositional Model Checking for Regular Timing Diagrams.- Vacuity Detection in Temporal Model Checking.- Formal Methods and Industrial Applications.- Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard.- Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors.- Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics.- Abstraction and Compositional Techniques.- From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking.- Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.- Abstract BDDs: A Technique for Using Abstraction in Model Checking.- Theorem Proving Related Approaches.- Formal Synthesis at the Algorithmic Level.- Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving.- Verification of Infinite State Systems by Compositional Model Checking.- Symbolic Simulation/Symbolic Traversal.- Formal Verification of Designs with Complex Control by Symbolic Simulation.- Hints to Accelerate Symbolic Traversal.- Specification Languages and Methodologies.- Modeling and Checking Networks of CommunicatingReal-Time Processes.- ”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation.- Program Slicing of Hardware Description Languages.- Posters.- Results of the Verification of a Complex Pipelined Machine Model.- Hazard—Freedom Checking in Speed—Independent Systems.- Yet Another Look at LTL Model Checking.- Verification of Finite-State-Machine Refinements Using a Symbolic Methodology.- Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars.- A Systematic Incrementalization Technique and Its Application to Hardware Design.- Bisimulation and Model Checking.- Circular Compositional Reasoning about Liveness.- Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell.- Exploiting Retiming in a Guided Simulation Based Validation Methodology.- Fault Models for Embedded Systems.- Validation of Object-Oriented Concurrent Designs by Model Checking.