Vor Ort
Merkzettel Warenkorb
  • Produktbild: Design of Energy-Efficient Application-Specific Instruction Set Processors
  • Produktbild: Design of Energy-Efficient Application-Specific Instruction Set Processors
- 10%

Design of Energy-Efficient Application-Specific Instruction Set Processors

10% sparen

95,99 € UVP 106,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

07.12.2010

Verlag

Springer Us

Seitenzahl

234

Maße (L/B/H)

25,4/17,8/1,5 cm

Gewicht

493 g

Auflage

Softcover reprint of the original 1st ed. 2004

Sprache

Englisch

ISBN

978-1-4419-5425-1

Beschreibung

Rezension

From the reviews:



"This book deals with the basic principles of design methodology that addresses the aspects of ASIP performance and energy optimizations. … The chapters of the book are concise and well written. The book is timely and well organized. It clearly gives an adequate view of the currently hottest topics in ASIP design. … The book should be of considerable interest for graduate-level students in Electrical and Computer Engineering, researchers, and specialists … . I would certainly like to fully recommend this book … ." (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

07.12.2010

Verlag

Springer Us

Seitenzahl

234

Maße (L/B/H)

25,4/17,8/1,5 cm

Gewicht

493 g

Auflage

Softcover reprint of the original 1st ed. 2004

Sprache

Englisch

ISBN

978-1-4419-5425-1

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

Ein neues Kapitel für Ihre Bücher

Ein neues Kapitel für Ihre Bücher

Schenken Sie Ihren alten Schätzen ein zweites Leben: Einfach Barcode scannen, Versandetikett ausdrucken, Bücher verschicken und Thalia Geschenkkarte erhalten.

Jetzt verkaufen
Jetzt verkaufen

Noch keine Bewertungen vorhanden

Verfassen Sie die erste Bewertung zu diesem Artikel

Helfen Sie anderen Kundinnen und Kunden durch Ihre Meinung.

Kundinnen und Kunden meinen

Bewertungen (0)
  • Produktbild: Design of Energy-Efficient Application-Specific Instruction Set Processors
  • Produktbild: Design of Energy-Efficient Application-Specific Instruction Set Processors
  • Foreword. Acknowledgements. About the Authors. I: Introduction. 2: Focus and Related Work. 2.1. Focus of this Work. 2.2. Previous Work. 2.3. Differences to Previous Work. 3: Efficient Low-Power Hardware Design. 3.1. Metrics of the Implementation and the Hardware Design Methodology. 3.2. Basics of Low-Energy Hardware Design. 3.3. Techniques to Reduce the Energy Consumption. 3.4. Concluding Remarks. 4: Application-Specific Processor Architectures. 4.1. Definitions of ASIP Related Terms. 4.2. ASIP Applications. 4.3. ASIP Design Space. 4.4. Critical Factors for Energy-Efficient ASIPs. 4.5. Concluding Remarks. 5: The ASIP Design Flow. 5.1. Example Applications. 5.2. Application Profiling and Partitioning. 5.3. Combined ASIP HW/SW Synthesis and Profiling. 5.4. Verification. 5.5. Concluding Remarks. 6: The ASIP Design Environment. 6.1. The LISA Language. 6.2. The LISA Design Environment. 6.3. Extensions to the LISA Design Environment. 6.4. Concluding Remarks. 7: Case Studies. 7.1. Case Study I: BVD-T Acquisition and Tracking. 7.2. Case Study II: Linear Algebra Kernels and Eigenvalue Decomposition. 7.3. Concluding Remarks. 8: Summary. A: ASIP Development Using LISA 2.0. A.1. The LISA 2.0 Language. A.2. Design Space Exploration. A.3. Design Implementation. A.4. Software Tools Generation. A.5. System Integration. A.6. Summary. B: Computational Kernels. B.1. The CORDIC Algorithm. B.2. FIR Filter. B.3. The Fast Fourier Transform. B.4. Vector/Matrix Operations. B.5. Complex EVD Using a Jacobi-like Algorithm. C: ICORE Instruction Set Architecture. C.1. Processor Resources. C.2. Pipeline Organization. C.3. Instruction Summary. C.4. Exceptions to the Hidden Pipeline Model. C.5. ICORE Memory Organization and I/O Space. C.6. Instruction Coding. D: Different ICORE Pipeline Organizations. E: ICORE HDL Description Templates. E.1. Generic Register File Entity. E.2. Generic Bit-Manipulation Unit. F: Area, Power and Design Time for ICORE. G: Acronyms. Bibliography.